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Features
* Stereo Audio DAC
2.7V to 3.3V Analog Supply Operation 2.4V to 3.3V Digital Supply Operation 20-bit Stereo Audio DAC 93 dB SNR Playback Stereo Channels 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls Stereo Line Level Input with Volume Control/mute and Playback through the Headset Drivers - Differential Monaural Auxiliary Input, with Volume Control/mute and Playback through the Headset Drivers - Accepts Mixed Signals from All Signal Paths (Line Inputs, External Mono and DAC Output) - 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates - 256x or 384xFs Master Clock Frequency - I2S Serial Audio Interface * Mono Audio Power Amplifier - Supply Input from Main Li-Ion Battery - 440mW on 8 Ohm Load - Low Power Mode for Earphone - Programmable Volume Control (-22 to +20 dB) - Fully Differential Structure, Input and Output - 8 mA Drain Current in Full Power Mode - Power-down mode (Consumption Less than 2uA) - Minimum External Components (Direct Connection of the Loudspeaker) * Applications: Mobile Phones, Digital Cameras, PDAs, SmartPhones, DECT Phones, Music Players - - - - - -
Power Management for Mobiles (PM) AT73C213 Audio Interface for Portable Handsets
1. Description
The AT73C213 is a fully integrated, low-cost, combined stereo audio DAC and audio power amplifier circuit targeted for Li-Ion or Ni-Mh battery powered devices such as mobile phones, smartphones, PDA, DECT phones, digital still cameras, music players or any other type of handheld device where an audio interface is needed. The stereo DAC section is a complete high performance, stereo audio digital-to-analog converter delivering a 93 dB dynamic range. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. This architecture provides a high insensitivity to clock jitter. The digital interpolation filter increases the sample rate by a factor of 8 using 3 linear phase half-band filters cascaded, followed by a first order SINC interpolator with a factor of 8. This filter eliminates the images of baseband audio, retaining only the image at 64x the input sample rate, which is eliminated by the analog post filter. Optionally, a dither signal can be added that reduces possible noise tones at the output. However, the use of a multibit sigma-delta modulator already provides extremely low noise tone energy. Master clock is from 256 or 384 times the input data rate, allowing choice of input data rate up to 50 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz. The DAC section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 Ohm headset pair of drivers.
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The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs, as well as a differential monaural auxiliary input (line level). The DAC output can be connected through a buffer stage to the input of the audio power amplifier, using 2x coupling capacitors The mono buffer stage also includes a mixer of the LINEL and LINER inputs, as well as a differential monaural auxiliary input (line level) which can be, for example, the output of a voice Codec output driver in mobile phones. The audio power amplifier is a dual-mode AB class amplifier with differential output and programmable volume control. In full power mode, it is capable of driving an 8-ohm loudspeaker at maximum power of 1W at 5V supply and 440 mW at 3.6V supply. In low power mode, it can drive the same loudspeaker as an earpiece, making it suitable as a handsfree speaker driver in wireless handset application. The volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio formats are digitally programmable via a 4-wire SPI bus and the digital audio data are provided through a multi-format I2S interface.
2. Block Diagram
Figure 2-1. AT73C213 Functional Block Diagram
AUXG: -33 to +12dB in 3dB step +20 dB and mute
MONO VBAT GNDB PAINP PAINN VREF AVDD LPHN HPN HPP CBP
AUXP
AT73C213
AUXN
LINER PGA
LLIG: -33 to +12dB in 3dB step + 20dB and mute
Voltage Reference
Audio PA
APAGAIN -22 to +20dB in 3dB step
Status Registers
VDIG SPI_DOUT
INGND LINEL PGA
RLIG: -33 to +12dB in 3dB step + 20dB and mute
SPI_DIN SPI SPI_CLK SPI_CSB
LOLC: -6 to +6dB in 3dB step
HSL VCM 32 driver + DAC
LLOG: -46.5dB to 0dB in 1.5dB step and mute
Volume Control +
LMPG: -34.5dB to +12dB in 1.5dB step and mute
Volume Control MCLK Serial Audio I/F RSTB SMODE SDIN LRFS BCLK
Digital Filter
ROLC: -6 to +6dB in 3dB step 32 driver HSR
AVDDHS MONOP MONO MONON
+
DAC
Volume Control
+
Volume Control
Digital Filter
RLOG: -46.5dB to 0dB in 1.5dB step and mute
+
RMPG: -34.5dB to +12dB in 1.5dB step and mute
GNDD
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3. Pin Description
Table 3-1.
Pin Name LPHN HPN VBAT HPP CBP PAINN PAINP SDIN BCLK LRFS MCLK RSTB SMODE GNDD VDIG SPI_DOUT SPI_DIN SPI_CLK SPI_CSB MONON MONOP AUXP AUXN VREF AVDD HSL HSR AVDDHS LINEL LINER INGND VCM GNDB
Pin Description
I/O O O I O O I I I I I I I I GND I O I/O I I O O I I I I O O I I I I I GND Pin 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 33 (Bottom) Type Analog Analog Supply Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Ground Supply Digital Digital Digital Digital Analog Analog Analog Analog Analog Supply Analog Analog Supply Analog Analog Analog Analog Ground Function Low power audio stage output Negative speaker output Audio amplifier supply Positive speaker output Audio amplifier common mode voltage decoupling Audio amplifier negative input Audio amplifier positive input Audio interface serial data input Audio interface bit clock Audio interface left/right channel synchronization frame pulse Audio interface master clock input Master reset (active low) Serial interface selection (to connect to ground) Digital ground Digital supply SPI data output SPI data input SPI clock SPI chip select Negative monaural driver output Positive monaural driver output Audio mono auxiliary positive input Audio mono auxiliary negative input Voltage reference pin for decoupling Analog supply (DAC + Line in + Aux + Mono out) Left channel headset driver output Right channel headset driver output Headset driver analog supply Left channel line in Right channel line in Line signal ground pin for decoupling Common mode reference for decoupling Analog ground
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4. Electrical Characteristics
Table 4-1. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature (Industrial)...............-40 C to +85 C Storage Temperature ................................... -55C to +150C Power Supply Input on VBAT.......................................................... -0.3V to +5.5V on VDIG, AVDD .............................................. -0.3V to +3.6V
5. Digital IOs
All the digital IOs: SDIN, BCLK, LRFS, MCLK, RSTB, SMODE, SPI_DOUT, SPI_DIN, SPI_CLK, SPI_CSB are referred to as VDIG. Table 5-1.
Symbol VIL VIH VOL VOH
Digital IOs
Parameter Low level input voltage High level input voltage Low level output voltage High level output voltage Conditions Guaranteed input low Voltage Guaranteed input high Voltage IOL = 2 mA IOH = 2 mA VDIG from 2.4Vto 3.3 V from 2.4Vto 3.3 V from 2.4Vto 3.3 V from 2.4Vto 3.3 V VDIG - 0.5V Min -0.3 0.8 x VDIG Max 0.2 x VDIG VDIG + 0.3 0.4 Unit V V V V
6. Audio Power Amplifier
6.1 Electrical Specifications
VBAT = 3.6V, TA = 25C unless otherwise noted. High power mode, 100 nF capacitor connected between CBP and GND Audio, 470 nF input capacitors, load = 8 Ohms. Table 6-1.
Parameter VDD IDD IDDstby VCbp VOS ZIN ZLFP ZLLP CL PSRR
Audio Power Amplifier Electrical Specifications
Symbol Supply voltage Quiescent current Standby current DC reference Output differential offset Input impedance Output load Output load Capacitive load Power supply rejection ratio 200 to 2 kHz differential output 60 Full gain Active state Full Power mode Low-Power mode, including R1 -20 12K 6 100 VDD/2 0 20k 8 150 20 30k 32 300 100 Conditions Unloaded, 100 nF decoupling capacitor to GND Inputs shorted, no load Min 3 Typ 3.6 6 Max 5.5 8 2 Unit V mA A V mV Ohm Ohm Ohm pF dB
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Table 6-1.
Parameter BWmin
Audio Power Amplifier Electrical Specifications
Symbol Low Frequency Cutoff Conditions 1 kHz reference frequency 3 dB attenuation 470 nF input coupling capacitors 1 KHz reference frequency 3 dB attenuation 470 nF input coupling capacitors Off to on mode Voltage already settled Input capacitors precharged Max gain, A weighted High power mode, VDD = 3.6V, 1 kHz, Pout = 100 mW, gain = 0dB Low power mode, VDD = 3.6V, 1KHz, Vout = 100m Vpp, Max gain, load 8 ohms in series with 200 ohms Low power mode, VDD = 3.6V, 1 KHz, Vout = 100 mVpp, Max gain, load 8 ohms in series with 200 ohms -2 -0.7 120 0.3 20 Min Typ 50 Max Unit Hz
BWmax
High Frequency Cutoff
kHz
tUP VN THDHP
Output setup time Output noise Output distortion
10 500
ms VRMS %
THDLP
Output distortion
1
%
Pmax GACC GSTEP
Maximum power Overall Gain accuracy Gain Step Accuracy
440 0 0 2 0.7
mW dB dB
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7. Audio DAC
7.1 Electrical Specifications
AVDD, AVDDHS = 2.8 V, TA = 25C, typical case, unless otherwise noted. All noise and distortion specifications are measured in the 20 Hz to 0.425xFs and A-weighted filtered. Full-scale levels scale proportionally with the analog supply voltage. Table 7-1. Electrical Specifications
Min OVERALL Operating Temperature (ambient) Analog Supply Voltage (AVDD, AVDDHS) Digital Supply Voltage (VDIG) DIGITAL INPUTS/OUTPUTS Resolution Logic Family Logic Coding ANALOG PERFORMANCE - DAC to Line-out/Headphone Output Output level for full scale input (for AVDD, AVDDHS = 2.8 V) Output common mode voltage Output load resistance (on HSL, HSR) Headphone load Line load Output load capacitance (on HSL, HSR) Headphone load Line load Signal to Noise Ratio (-1dBFS @ 1kHz input and 0dB Gain) Line and Headphone loads Total Harmonic Distortion (-1dBFS @ 1kHz input and 0dB Gain) Line Load Headphone Load Headphone Load (16 Ohm) Dynamic Range (measured with -60 dBFS @ 1kHz input, extrapolated to full-scale) Line Load Headphone Load Interchannel mismatch Left-channel to right-channel crosstalk (@ 1kHz) Output Headset Driver Level Control Range Output Headset Driver Level Control Step -6 3 87 1.65 0.5 x AVDDHS 16 7 32 10 30 30 92 1000 150 Vpp V 20 CMOS 2's Complement bits -40 2.7 2.4 +25 2.8 2.8 +85 3.3 3.3 C V V Typ Max Units
Ohm kOhm pF pF dB
0.01 0.06 0.5
0.016 0.1 1
% % %
88 70
93 74 0.1 -90 1 -80 6
dB dB dB dB dB dB
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Table 7-1. Electrical Specifications (Continued)
Min PSRR 1 kHz 20 kHz Maximum output slope at power up (100 to 220 F coupling capacitor) ANALOG PERFORMANCE - Line-in/Microphone Input to Line-out/Headphone Output Input level for full scale output - 0dBFS Level @ AVDD, AVDDHS = 2.8 V and 0 dB gain @ AVDD, AVDDHS = 2.8 V and 20 dB gain Input common mode voltage Input impedance Signal to Noise Ratio -1 dBFS @ 1kHz input and 0 dB gain -21 dBFS @ 1kHz input and 20 dB gain Dynamic Range (extrapolated to full scale level) -60 dBFS @ 1kHz input and 0 dB gain -60 dBFS @ 1kHz input and 20 dB gain Total Harmonic Distortion -1dBFS @ 1kHz input and 0 dB gain -1dBFS @ 1kHz input and 20 dB gain Interchannel mismatch Left-channel to right-channel crosstalk (@ 1kHz) ANALOG PERFORMANCE - Differential mono input amplifier Differential input level for full scale output - 0dBFS Level @ AVDD, AVDDHS = 2.8 V and 0 dB gain Input common mode voltage Input impedance Signal to Noise Ratio (-1 dBFS @ 1kHz input and 0 dB gain) Total Harmonic Distortion (-1dBFS @ 1kHz input and 0 dB gain) ANALOG PERFORMANCE - PA Driver Differential output level for full scale input (for AVDD, AVDDHS = 2.8 V) Output common mode voltage 3.3 0.5 x AVDDHS 10 Output load 30 Signal to Noise Ratio (-1dBFS @ 1kHz input and 0dB Gain) 76 80 pF dB Vppdif V kOhm 7 76 1.65 583 0.5xAVDD 10 80 -85 -81 Vppdif mVrms V kOhm dB dB 7 1.65 583 0.165 58.3 0.5 x AVDD 10 85 71 86 72 0.01 0.018 0.1 -90 0.016 0.04 1 -80 Vppm Vrms Vppm Vrms V kOhm Typ 55 50 3 Max Units dB dB V/s
81
dB
82
dB
% % dB dB
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Table 7-1.
Electrical Specifications (Continued)
Min Typ -75 Max -71 Units dB
Total Harmonic Distortion (-1dBFS @ 1kHz input and 0dB Gain) MASTER CLOCK Master Clock Maximum Long Term Jitter DIGITAL FILTER PERFORMANCE Frequency response (10 Hz to 20 kHz) Deviation from linear phase (10 Hz to 20 kHz) Passband 0.1 dB corner Stopband Stopband Attenuation DE-EMPHASIS FILTER PERFORMANCE (for 44.1kHz Fs) MAX deviation from ideal response POWER PERFORMANCE Current consumption from Analog supply in power on Current consumption from Analog supply in power down Power on Settling Time From full power down to full power up (Vref and VCM decoupling capacitors charge) Line in amplifier (line in coupling capacitors charge) Driver amplifier (out driver DC blocking capacitors charge) -1 0.5465 65
1.5
nspp
0.1 0.1 0.4535
dB deg Fs Fs dB
1
dB
9.5 10 500 50 500
mA mA ms ms ms
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7.2 Digital Filters Transfer Function
Figure 7-1. Channel Filter
Figure 7-2.
Channel Filter
Figure 7-3.
De-emphasis Filter
FR of DAC Decimator with Deemphasis Fs=44100; OSR=128 0
-2
-4
Gain (dB)
-6
-8
-10
-12 10
3
10 Frequency (Hz)
4
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7.3
Data Interface
Normal operation is entered by applying correct LRFS, BCLK and SDIN waveforms to the serial interface, as illustrated in Figure 7-4, Figure 7-5 and Figure 7-6. To avoid noise at the output, the reset state is maintained until proper synchronization is achieved in the serial interface. The data interface allows three different data transfer modes. See Figure 7-4, Figure 7-5 and Figure 7-6.
Figure 7-4.
BCLK
20-bit I2S Justified Mode
LRFS
SDIN
R1
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
Figure 7-5.
BCLK
20-bit MSB Justified Mode
LRFS
SDIN
R0
L(N-1)
L(N-2)
L(N-3)
...
L2
L1
L0
R(N-1)
R(N-2)
R(N-3)
...
R2
R1
R0
L(N-1)
Figure 7-6.
BCLK
20-bit LSB Justified Mode
LRFS
SDIN
R0
L(N-1)
L(N-2)
...
L1
L0
R(N-1)
R(N-2)
...
R1
R0
L(N-1)
The selection between modes is done using the DINTSEL<1:0> signal.
DINTSEL <1:0> 00 01 1x Format I2S Justified MSB Justified LSB Justified
The data interface always works in slave mode. This means that the LRFS and the BCLK signals are provided by the host controller. In order to achieve proper operation, the LRFS and the BCLK signals must be synchronous with the MCLK master clock signal and their frequency relationship must reflect the selected data mode. For example, if the data mode selected is the 20bit MSB Justified, then the BCLK frequency must be 40 times higher than the LRFS frequency.
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7.4 Timing Specifications
Data Interface Timing Diagram
1 N 19N+1 20N M/2.N+1 M/2.(N+1) (M-1).N+1 M.N
Figure 7-7.
MCLK
td1
1
20
M/2+1
M
BCLK
td2
LRFS
ts3 th3
SDIN
Table 7-2.
Data Interface Timing Parameters
Parameter Min 2.5 0 10 10 Typ Max 7.5 5 Unit ns ns ns ns
td1 td2 ts3 th3
Delay from MCLK rising edge to BCLK edges Delay from BCLK falling edge to LRFS edges din set-up time before BCLK rising edge din hold time after BCLK rising edge
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8. SPI Interface
8.1 Architecture
The SPI is a three-wire bi-directional asynchronous serial link. It works only in slave mode. The protocol is the following: Figure 8-1. SPI Architecture
SPI_CSB
SPI_CLK
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
SPI_DIN
d7 d6 d5 d4 d3 d2 d1 d0
SPI_DOUT
8.2
SPI Protocol
On SPI_DIN, the first bit is a read/write bit. 0 indicates a write operation, while 1 is for a read operation. The seven following bits are used for the register address and the eight last ones are the write data. For both address and data, the most significant bit is the first one. In case of a read operation, SPI_DOUT provides the contents of the read register, MSB first. The transfer is enabled by the CSB signal active low. When no operation is being carried out, SPI_DOUT is set high impedance to allow sharing of MCU serial interface with other devices. The interface is reset at every rising edge of SPI_CSB in order to come back to an idle state, even if the transfer does not succeed. The SPI is synchronized with the serial clock SPI_CLK. Falling edge latches SPI_DIN input and rising edge shifts SPI_DOUT output bits. Note that MCLK must run during any SPI write access from address 0x00 to 0x0D.
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8.3 SPI Interface Timing
SPI Timing
SPI_CSB
Tssen Twl Tc Thsen
Figure 8-2.
SPI_CLK
Twh Tssdi Thsdi
SPI_DIN
Tdsdo
Thsdo
SPI_DOUT
Table 8-1.
Parameter Tc Twl Twh Tssen Thsen Tssdi Thsdi Tdsdo Thsdo
SPI Timing Parameters
Description SPI_CLK min period SPI_CLK min pulse width low SPI_CLK min pulse width high Setup time SPI_CSB falling to SPI_CLK rising Hold time SPI_CLK falling to SPI_CSB rising Setup time SPI_DIN valid to SPI_CLK falling Hold time SPI_CLK falling to SPI_DIN not valid Delay time SPI_CLK rising to SPI_DOUT valid Hold time SPI_CLK rising to SPI_DOUT not valid Min 100 ns 50 ns 50 ns 50 ns 50 ns 20 ns 20 ns 0 ns Max 20 ns -
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8.4
SPI User Interface
SPI Register Mapping
Register DAC_CTRL DAC_LLIG DAC_RLIG DAC_LPMG DAC_RPMG DAC_LLOG DAC_RLOG DAC_OLC DAC_MC DAC_CSFC DAC_MISC DAC_PRECH DAC_AUXG DAC_RST PA_CRTL Note: Name DAC Control DAC Left Line In Gain DAC Right Line In Gain DAC Left Master Playback Gain DAC Right Master Playback Gain DAC Left Line Out Gain DAC Right Line Out Gain DAC Output Level Control DAC Mixer Control DAC Clock and Sampling Frequency Control DAC Miscellaneous DAC Precharge Control DAC Auxiliary Input Gain Control DAC Reset Power Amplifier Control MSB = Bit 7, LSB = Bit 0 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00 0x05 0x05 0x08 0x08 0x00 0x00 0x22 0x09 0x00 0x00 0x00 0x05 0x00 0x00
Table 8-2.
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0C 0x0D 0x10 0x11
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8.5 DAC Control Register
Register Name: DAC_CTRL Reset State: 0x00 Access: Read/Write
7 ONPADRV
6 ONAUXIN
5 ONDACR
4 ONDACL
3 ONLNOR
2 ONLNOL
1 ONLNIR
0 ONLNIL
* ONLNIL Left channel line in amplifier (L to power down, H to power up) * ONLNIR Right channel line in amplifier (L to power down, H to power up) * ONLNOL Left channel line out driver (L to power down, H to power up) * ONLNOR Right channel line out driver (L to power down, H to power up) * ONDACL Left channel DAC (L to power down, H to power up) * ONDACR Right channel DAC (L to power down, H to power up) * ONAUXIN Differential mono auxiliary input amplifier (L to power down, H to power up) * ONPADRV Differential mono PA driver (L to power down, H to power up)
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8.6
DAC Left Line In Gain Register
Register Name: DAC_LLIG Reset State: 0x05 Access: Read/Write
7 0
6 0
5 0
4
3
2 LLIG
1
0
* LLIG: Left channel line in analog gain selector
LLIG<4:0> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Gain 20 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 < -60 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.7 DAC Right Line In Gain Register
Register Name: DAC_RLIG Reset State: 0x05 Access: Read/Write
7 0
6 0
5 0
4
3
2 RLIG
1
0
* RLIG: Right channel line in analog gain selector
RLIG<4:0> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Gain 20 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 < -60 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.8
DAC Left Master Playback Gain Register
Register Name: DAC_LMPG Reset State: 0x08 Access: Read/Write
7 0
6 0
5
4
3 LMPG
2
1
0
* LMPG: Left channel master playback digital gain selector
LMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 Gain 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.9 DAC Right Master Playback Gain Register
Register Name: DAC_RMPG Reset State: 0x08 Access: Read/Write
7 0
6 0
5
4
3 RMPG
2
1
0
* RMPG: Right channel master playback digital gain selector
RMPG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 Gain 12.0 10.5 9.0 7.5 6.0 4.5 3.0 1.5 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB RMPG<5:0> 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.10
DAC Left Line Out Gain Register
Register Name: DAC_LLOG Reset State: 0x00 Access: Read/Write
7 0
6 0
5
4
3 LLOG
2
1
0
* LLOG: Left channel line out digital gain selector
LLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Gain 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LLOG<5:0> 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.11 DAC Right Line Out Gain Register
Register Name: DAC_RLOG Reset State: 0x00 Access: Read/Write
7 0
6 0
5
4
3 RLOG
2
1
0
* RLOG: Right channel line out digital gain selector
RLOG<5:0> 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 Gain 0.0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB RLOG<5:0> 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 Gain -24.0 -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 mute Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.12
DAC Output Level Control Register
Register Name: DAC_OLC Reset State: 0x22 Access: Read/Write
7 RSHORT
6
5 ROLC
4
3 LSHORT
2
1 LOLC
0
* LOLC: Left channel output level control selector
LOLC 000 001 010 011 100 Gain 6 3 0 -3 -6 Unit dB dB dB dB dB
* LSHORT: Left channel short circuit indicator Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation. * ROLC: Right channel output level control selector
ROLC 000 001 010 011 100 Gain 6 3 0 -3 -6 Unit dB dB dB dB dB
* RSHORT: Right channel short circuit indicator Persistent; after being set, bit is not cleared automatically even after the short circuit is eliminated; must be cleared by reset cycle or direct register write operation.
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8.13 DAC Mixer Control Register
Register Name: DAC_MC Reset State: 0x09 Access: Read/Write
7 0
6 0
5 INVR
4 INVL
3 RMSMIN2
2 RMSMIN1
1 LMSMIN2
0 LMSMIN1
* LMSMIN1: Left Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) * LMSMIN2: Left Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) * RMSMIN1: Right Channel Mono/Stereo Mixer Left Mixed input enable (H to enable, L to disable) * RMSMIN2: Right Channel Mono/Stereo Mixer Right Mixed input enable (H to enable, L to disable) * INVL: Left channel mixer output invert (H to enable, L to disable) * INVR: Right channel mixer output invert (H to enable, L to disable) 8.13.1 Digital Mixer Control The Audio DAC features a digital mixer that allows the mixing and selection of multiple input sources. The mixing/multiplexing functions are described in Figure 8-3 and Table 8-3. Figure 8-3. Digital Mixer Functions
Left channel
Volume Control
+
2
1
Volume Control
From digital filters
To DACs 1
Volume Control
+
2
Volume Control
Right channel
Note:
When the two mixer inputs are selected, a -6 dB gain is applied to the output signal. When only one input is selected, no gain is applied.
Table 8-3.
Signal LMSMIN1 LMSMIN2 RMSMIN1 RMSMIN2
Digital Mixer Signal Description
Description Left Channel Mono/Stereo Mixer Left Mixed input enable - High to enable, Low to disable Left Channel Mono/Stereo Mixer Right Mixed input enable - High to enable, Low to disable Right Channel Mono/Stereo Mixer Left Mixed input enable - High to enable, Low to disable Right Channel Mono/Stereo Mixer Right Mixed input enable - High to enable, Low to disable
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8.14
DAC Clock and Sampling Frequency Control Register
Register Name: DAC_CSFC Reset State: 0x00 Access: Read/Write
7 0
6 0
5 0
4 OVRSEL
3 0
2 0
1 0
0 0
* OVRSEL: Master clock selector L to 256 x Fs, H to 384 x Fs Master clock and sampling frequency selection Table 8-4 describes the modes available for master clock and sampling frequency selection. Table 8-4.
OVRSEL 0 1
Master Clock Modes
Master Clock 256 x Fs 384 x Fs
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8.15 DAC Miscellaneous Register
Register Name: DAC_MISC Reset State: 0x00 Access: Read/Write
7 VCMCAPSEL
6 0
5 DINTSEL
4
3 DITHEN
2 DEEMPEN
1 NBITS
0
* NBITS<1:0>: Data interface word length The selection of input sample size is done using the NBITS field.
NBITS <1:0> 00 01 10 Format 16 bits 18 bits 20 bits
* DEEMPEN: De-emphasis enable (L to disable, H to enable) To enable the de-emphasis filtering the DEEMPHEN signal must be set to high. * DITHEN: Dither enable (L to disable, H to enable) The dither option (added in the playback channel) is enabled by setting the DITHEN signal to high. * DINTSEL<1:0>: I2S data format selector The selection between modes is done using the DINTSEL<1:0> signal.
DINTSEL<1:0> 00 01 1x Format I2S Justified MSB Justified LSB Justified
* VCMCAPSEL: VCM decoupling capacitor selector L for 10 F, H for 100 F
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8.16
DAC Precharge Control Register
Register Name: DAC_PRECH Reset State: 0x00 Access: Read/Write
7
PRCHGPDRV
6
PRCHGAUX1
5
PRCHGLNOR
4
PRCHGLNOL
3
PRCHGLNIR
2
PRCHGLNIL
1
PRCHG
0
ONMSTR
* ONMSTR: Master power on control (L to power down, H to power up) * PRCHARGE: Master pre-charge (H to charge) * PRCHARGELNIL: Left channel line in pre-charge (H to charge) * PRCHARGELNIR: Right channel line in pre-charge (H to charge) * PRCHARGELNOL: Left channel line out pre-charge (H to charge) * PRCHARGELNOR: Right channel line out pre-charge (H to charge) * PRCHARGEAUXIN: Differential mono auxiliary input pre-charge (H to charge) * PRCHARGEPADRV: Differential mono PA driver pre-charge (H to charge)
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8.17 DAC Auxiliary Input Gain Control Register
Register Name: DAC_AUXG Reset State: 0x05 Access: Read/Write
7 0
6 0
5 0
4
3
2 AUXG
1
0
* AUXG: Differential mono auxiliary input analog gain selector
AUXG<4:0> 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Gain 20 12 9 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 < -60 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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8.18
DAC Reset Register
Register Name: DAC_RST Reset State: 0x00 Access: Read/Write
7 -
6 -
5 -
4 -
3 -
2 RESMASK
1 RESFILZ
0 RSTZ
* RSTZ: Active low reset of the audio codec * RESFILZ: Active low reset of the audio codec filter * RESMASK: Active high reset mask of the audio codec See "Supplies and Start-up" on page 30.
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8.19 PA Control Register
Register Name: PA_CTRL Reset State: 0x00 Access: Read/Write
7 -
6 APAON
5 APAPRECH
4 APALP
3
2 APAGAIN
1
0
* APAGAIN<3:0>: Audio power amplifier gain
APAGAIN<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 Gain (db) -22 20 17 14 11 8 5 2 APAGAIN<3:0> 1000 1001 1010 1011 1100 1101 1110 1111 Gain (db) -1 -4 -7 -10 -13 -16 -19 -22
* APALP: Audio power amplifier low power bit 0: High power 1: Low power * APAPRECH: Audio power amplifier precharge bit * APAON: Audio power amplifier on bit
APAON 0 0 1 1 APAPRECH 0 1 0 1 Operating Mode Stand-by Input capacitors precharge Active mode Forbidden state
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9. Supplies and Start-up
In operating mode, VBAT (supply of the audio power amplifier) must be between 3V and 5.5V and AVDD, AVDDHS and VDIG must be inferior or equal to VBAT. A typical application is VBAT connected to a battery and AVDD, AVDDHS and VDIG supplied by regulators. VBAT must be present at the same time or before AVDD, AVDDHS and VDIG. RSTB must be active (0) until the voltages are stable and reach the proper values. To avoid noise issues, it is recommended to use ceramic decoupling capacitors for each supply close to the package. See Figure 11-1 on page 32. The track of the supplies must be optimized to minimize the resistance, especially on VBAT where all the current from the power amplifier comes from. HPN and HPP must be routed symmetrically and the resistance must be minimized.
9.1
Audio DAC Start-up Sequences
In order to minimize the noise during the start-up, a specific sequence should be applied.
9.1.1
Power on Example Path DAC to headset output 1. Write @0x10 => 0x03 (deassert the reset) 2. Write @0x0C => 0xFF (precharge + master on) 3. Write @0x00 => 0x30 (ONLNOL and ONLONOR set to 1) 4. Delay 500 ms 5. Write @0x0C => 0x01 (precharge off + master on) 6. Delay 1ms 7. Write @0x00 => 0x3C (ONLNOL, ONLNOR, ONDACR and ONDACL set to 1)
9.1.2
Power off Example 1. Write @0x00 => 0x30 (ONDACR and ONDACL set to 0) 2. Write @0x0C => 0x00 (master off) 3. Delay 1ms 4. Write @0x00 => 0x00 (all off)
9.1.3
I2S Example In order to prevent I2S from generating noise at the output (for example a MP3 player switching from one song to another): 1. Set ONDAC to 0 ((bit 4 and 5 in register @0x00) 2. Stop I2S and MCLK When I2S is restarted, in order to prevent noise generation at the output: 1. Start MCLK 2. Write @0x10 => 0x07 (RSTMSK=1) 3. Write @0x10 => 0x04 (RESFILZ=0, RSTZ=0) 4. Write @0x10 => 0x07 (RESFILZ=1, RSTZ=1)
30
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5. Write @0x10 => 0x03 (RSTMSK=0) 6. Delay 5 ms 7. Set ONDAC to 1 (bit 4 and 5 in register @0x00) 8. Reprogram all DAC settings (Audio format, gains, etc.) 9. Start I2S.
9.2
Audio Power Amplifier Power on Sequence
To avoid an audible "click" at start-up, the input capacitors must be pre-charged before the power amplifier. 1. At start-up, set APAON off, APAGAIN<3:0> set to -22 dB, set APAPRECHARGE to 1. 2. Wait 50 ms minimum. 3. Then disable APAPRECH and set APAON. 4. Wait 10 ms min time. 5. Set the gain to the value chosen.
9.2.1
Audio Power Amplifier Power off Sequence To avoid an audible "click" at power-off, the gain should be set to the minimum gain (-22 dB) before turning off the power amplifier.
10. Current Consumption in Different Modes
Table 10-1.
Mode 0: Off 1: Standby 2: DAC Playback through Stereo Headset (Current in the load not included) 3: Stereo DAC Playback to Audio PA (Current in the load not included) 4: Playback from Mono in to Audio PA (Current in the load not included) 5: Playback from Stereo Line Input to Stereo Headset (Current in the load not included)
Current Consumption in Different Modes
Current Consumption (typ) 5 250 5100 9500 6200 1600 Current Consumption (max) 12 350 6700 13500 10500 3300 Unit uA uA uA uA uA uA
31
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11. Application Diagram
Figure 11-1. Application Using One Li-Ion Battery
PAINN 22u Battery (Li-Ion or 3 x NiMh or NiCd) VBAT 100n C16 CBP C7 8 8 Ohm Loudspeaker HPN 200 C15 R1 PAINP 470n MONOP 470n MONON R stereo line input (e.g. FM Radio) mono differential input 32 32 Ohm Headset 32 or Line Out 100u 10u INGND C10 GNDB GNDD 100u C5 HSL mono input (-) C6 C1 470n AUXN C4 L 470n mono input 470n (+) C3 LINEL 470n C12 C8 LINER SPI_DOUT SPI_DIN SPI_CLK AUXP SPI VCM 10u C11 C9 AVDD HPP C18
AT73C213
2.8V from LDO VDIG C17 100n 2.8V from LDO
3.6 V
Audio PA
AVDDHS
100n
LPHN
C19 100n
REF
VREF 10u
DIG
SPI_CSB SMODE RSTB MCLK Reset active low
HSR
Audio DAC
SDIN LRFS BCLK I2S
32
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12. Package Drawing
Figure 12-1. Package Outline
Notes:
1. All dimensions are in mm. 2. Drawing is for general information only. Refer to JEDEC drawing MO-220 for additional information.
Figure 12-2. Package Drawing with Pin 1 and Marking
... 31 32
AT73C213 YY WW XXXXXXXXX
1 2 ...
33
33
2744A-PMGMT-27-Jan-05 2744A-PMGMT-27-Jan-
13. Revision History
Table 13-1.
Doc. Rev. 2744A
Revision History
Date 27-Jan-05 Comments First issue. Change Request Ref.
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